Using the workspace
Workspace guide
The views of a project: Workflow, Code, Logic, Firmware, Assembly, C programs, Board (FPGA projects), Goals, and the Files panel.
Project views#
| View | What it is for |
|---|---|
| Workflow | How your design is built. Four sections: Map (the flow, first), Runs (the latest run's summary and the run history; the count is stages that need attention), Readiness (evidence across targets), and Setup (where it runs, process, single tool runs and the files tools need such as a Liberty library or an LVS reference, memories, SoC, package, shuttle; the chips beside the sections show the current setup and open it). Select a stage on the map to open its details beside it: the files it used and produced and who made them, open or protect those files, and rerun just that stage or everything after it. Focus shows the map across the whole window; Esc closes the details, then focus. Project history shows every checkpoint and lets you restore files. |
| Code | Browse and edit project files in the browser editor (details below). |
| Logic | Inspect the synthesized logic structure when a compatible netlist or design representation is available. The physical layout view displays routed layout artifacts when produced. |
| Board | FPGA projects only: using the real board. Program it with the built bitstream, see which LEDs, buttons, and connectors the design uses, read its serial output in the browser, and see hardware test results. The build itself (resources, timing, pins, bitstream) stays in Workflow. |
| Firmware | Shows what this design can run. Hardware that runs no programs (fixed-function logic, accelerators, sensors, and similar) says so and points to Workflow and Evaluation. For a CPU, press Set up this CPU once: Tapeo writes a testbench for your CPU, finds its instruction set and memory map, and runs a built-in instruction test and C self-tests. |
| Assembly | For CPUs. Write a program (or pick an example), press Build and run, and read the UART console, GPIO writes, and cycle count. Add your own tests as tests/name.S with the exact expected output in tests/name.expected. |
| C programs | For RISC-V CPUs whose status is Assembly + C ready. Write C with printf, press Build and run, and read the output. Builds never replace your CPU's program.hex unless you choose Install in boot ROM. |
| Goals | Are your goals met? Create numeric or behavior goals, edit saved goals, prepare tool-backed verification plans, run plans, and inspect results. Each measured result links to the Workflow stage that produced it. |
Code and the editor#
- Browse and edit project files in the browser editor. HDL, testbench, Tcl, SDC, Markdown, and other text files are shown as project-relative files. Markdown files can be previewed.
- Drag the right edge of the Files panel to make it wider; the width is remembered.
- The bar above the editor shows the file's folder path, type, line count, and who changed it last (your edit, AI, or a tool).
- Files the Architect changed last show an AI badge. A file you edit is protected from automatic AI repairs (Protect from AI in the toolbar shows and toggles this).
- In Code, Run testbench runs the project testbench on the current files; its waveform opens in the waveform viewer below. With a Python (cocotb) test file open, it runs that file (see Python testbenches).
- Under Simulation, Find an example takes a condition such as
full && pushand opens a waveform where it happens, found from reset without a testbench (see Find an example). - A saved waveform file (.vcd), such as a formal counterexample or a found example, opens in the waveform viewer instead of as text.
Files panel#
Create files and folders, organize the virtual project tree, open files for editing, download the project ZIP, and access the engineering handoff archive from Workflow. Save checkpoint (with an optional name) and Project history are in the project header.
Upload files (the arrow above the tree, or drop files on the tree) adds design files to the project: Verilog, SystemVerilog, VHDL, SystemRDL, SDC, Tcl, memory images, .f file lists, and tapeo.json, Python test files (.py, to tb/), up to 20 files and 300 KB at a time. A file goes to the usual folder for its kind (rtl/, tb/, constraints/, analysis/); the arrow on a folder puts it there. Before saving, the list shows where each file goes and which existing files it replaces. Uploaded files are yours, so the Architect does not overwrite them. Each file action gets its own checkpoint name in Project history, such as "Created rtl/fifo.sv" or "Uploaded 2 files".