SoC composition

A SoC's peripherals are reached through registers at fixed addresses on a bus. Tapeo builds that part from a description of the registers, using PeakRDL, the open-source SystemRDL tool set. Experimental.

Describe the map#

Write the registers in SystemRDL (the industry's register description language) and name the top map and the bus in soc/soc.json. The Architect can write both from a description.

{
  "name": "demo_soc",
  "rdl": "soc/soc.rdl",
  "bus": "apb4"
}

`include "gpio.rdl"
addrmap demo_soc {
  external gpio gpio0 @ 0x0000;   // a register block of its own
  external mem { mementries = 64; memwidth = 32; sw = rw; } scratch @ 0x3000;   // a port for your logic
  reg { field { sw = r; hw = na; } value[32] = 32'h0001_0000; } version @ 0x4000;
};

• Bus: axi4-lite, apb4, or wishbone (pipelined).
• Each external block with registers becomes its own register block. An external memory or block without registers becomes a request port for your own logic. Registers placed directly in the top map live in the bus block.
• The SystemRDL compiler checks the map: overlapping or misaligned blocks are rejected with the file and line.

Generate and check#

Press Generate the SoC in the Workflow tab, or run tapeo check soc (VS Code: Tapeo: Run a Check Now, then SoC). It takes about 15 seconds.

1. 1
   PeakRDL

   Generates the bus block with the address decoder, one register block per peripheral type, and the C header.
2. 2
   The top module

   Tapeo wires them into <name>_top with a named port for every hardware field (for example gpio0_data_out_value), then converts the SystemVerilog to plain Verilog (generated/soc/<name>.v) so every later stage can read it.
3. 3
   Register checks

   A generated testbench reads every register's reset value, writes and reads back every read-write field with its own pattern, checks the hardware outputs, drives the hardware inputs, sets and clears write-1-to-clear flags, and reads every field again at the end so two registers that share storage are caught.
4. 4
   FuseSoC

   A FuseSoC core (generated/soc/<name>.core), which FuseSoC reads to confirm it, so the SoC can be built outside Tapeo.

The SoC composition panel shows the address map, the checks, and the files; readiness has a SoC registers and bus section. tapeo soc prints the same.

Connect it#

• Instantiate <name>_top in your design. Its bus port covers addresses 0 to the map's size; a processor decodes its own upper address bits.
• Software includes generated/soc/<name>.h for the register offsets and fields.
• A project with tapeo.json lists generated/soc/<name>.v in its sources; without one it is picked up automatically.

What it is not#