Glossary

Terms#

RTL / HDL

The code that describes the digital hardware, usually Verilog or SystemVerilog.

Testbench

A simulation program that drives inputs into the design and checks its outputs.

Lint

A quick check of the RTL's structure (syntax, widths, latches) before simulation.

Code coverage

How much of the design the testbench exercised: lines that ran, branches taken, signals that changed.

Synthesis

Converts RTL into a gate-level logic representation.

Liberty file

A standard-cell library description used for cell mapping and timing characteristics.

SDC

Timing constraints such as clocks and input/output delays.

PDK

A process design kit: technology files and rules needed to design for a particular manufacturing process.

GDS

A geometric layout database commonly used to represent physical chip shapes.

DRC

Design-rule checking: tests layout geometry against a rule deck.

LVS

Layout-versus-schematic: compares a netlist extracted from layout with a reference netlist.

SPEF / parasitics

Estimated resistance and capacitance of routed wires, used for more realistic timing analysis.

Bitstream

The file that configures an FPGA board to become your design.

IP core

A ready-made, reusable block of hardware, such as a UART or a FIFO. Tapeo Hub holds verified ones.

Words in a run's story

The run bar's story underlines these words until you have opened them once.

Lint

A proof-reader for hardware code. It finds typos, wires of the wrong width, and signals nothing drives, in seconds, before anything runs.

Gate-level simulation

Your test run again on the real logic gates instead of your code, to catch differences between what you wrote and what was built.

Simulation

Running your design in software, one clock tick at a time, while a test feeds it inputs and checks its outputs. The record of every signal is the waveform.

Testbench

The test for your design: code that plays with its inputs and checks that its outputs are right.

Coverage

How much of your code the test actually tried. A line the test never reached could still hide a mistake.

CDC (clock-domain crossing)

A signal going from a part run by one clock to a part run by another. Without a small safety circuit (a synchronizer) it can be read half-changed.

RDC (reset-domain crossing)

Like a clock crossing, but between parts reset by different reset signals. One part can wake up while the other is still resetting.

FSM (state machine)

Logic that moves between named steps (states), such as IDLE, SEND, DONE. A state it can never reach usually means a mistake.

Constraints

Instructions for the build tools: how fast each clock runs and when signals arrive at the pins. The tools use them to judge whether the design is fast enough.

Formal proof

Instead of trying some inputs like a test, a prover checks every possible input and shows that a rule can never be broken.

Assert

A rule written into your design, such as "the count never goes above 9". Tests and proofs check it.

Counterexample

An example the prover found that breaks a rule: the inputs, cycle by cycle, shown as a waveform.

Equivalence check

A proof that the built circuit does exactly what your code says, for every input.

Synthesis

Turning your code into real logic gates and flip-flops from the chip's cell library. The number of cells is your design's size.

Netlist

Your design as a list of gates and the wires between them: what synthesis produces and the layout is built from.

Flip-flop

A one-bit memory that takes a new value on each clock tick. Counters, registers, and state machines are made of them.

Slack

Time to spare: how much earlier a signal arrives than the next clock tick needs. Negative slack means it is too slow.

Place and route

Putting every gate at a spot on the chip, then drawing the metal wires between them, layer by layer.

DRC (design rules)

The factory's rules for the drawing, such as how thin a wire may be and how close two wires may get. Breaking one means the chip may not be made reliably.

Extraction

Reading the circuit back from the drawn shapes: which transistors and wires the layout really makes.

LVS (layout versus schematic)

Checking that the circuit read back from the layout is exactly your design, with no missing or extra connections.

ERC (electrical rules)

A check for electrical mistakes, such as a transistor input left floating or two supplies touching.

Antenna effect

A long wire can collect electric charge while the chip is being made and damage the transistor it connects to. Small diodes fix it.

Bitstream

The file that programs an FPGA board to become your circuit.

Mutation testing

Planting small bugs in your design on purpose to see whether your test notices. Bugs it misses show where the test is weak.

See also

What results mean for how far each result goes.