Platform and account
Tools and technology platforms
Which tools Tapeo runs for you, which processes it knows, and what each process needs for layout and signoff.
Integrated tools#
| Step | Tool |
|---|---|
| RTL lint | Verilator |
| Simulation | Icarus Verilog |
| Synthesis and mapping | Yosys |
| Timing | OpenSTA |
| Physical design | OpenROAD |
| Signoff-related | KLayout, Magic, Netgen |
| Software workflows | RISC-V toolchain |
- Integrated tools are enabled for every user; Tapeo manages shared runner images and starts isolated jobs automatically.
- A runner can still be unavailable when the server is not configured or its image is missing.
Technology platforms#
Platforms represented in the app: SkyWater 130 HD/HS, GF180 MCU, IHP SG13G2, educational Nangate45, and ASAP7 manual/multi-library setup.
Note
A platform record or bundled runner resource does not mean every check is supported for that process.
Liberty libraries and corners#
- Yosys uses one selected Liberty file to map generic logic into standard cells.
- OpenSTA can analyze multiple compatible Liberty corners when the project timing Tcl loads the selected libraries, defines and evaluates a timing scene for each corner, and reports measurements tagged with each scene name.
- Workflow shows how many compatible corner files were inputs separately from which corners produced measurements.
- Uploading or selecting several libraries alone does not run multi-corner analysis.
Process data for layout and signoff#
Physical design and signoff also depend on process-specific data such as LEF/GDS libraries, technology files, DRC rule decks, extraction rules, and LVS setup. These files must correspond to the same process and release.
- Bundled exploratory decks may cover only part of the rules.
- KLayout DRC has a 30-minute default timeout and can be configured up to 60 minutes; a timeout or missing report remains unknown rather than zero.
- When no reference netlist is attached, workflow can freshly synthesize one from the saved RTL and matching Liberty before LVS. Gate-level Verilog references use the matching standard-cell SPICE/CDL library.
- Referenced hard macros declared by the selected process pack are compared as pin-compatible blackboxes at the layout boundary to avoid expanding large memories; this does not validate macro internals.
- Magic duplicate-cell and electrically-shorted-port warnings are surfaced for review; they do not by themselves establish a clean extraction.