Tapeo

Design features

VHDL

Write the design and its testbench in VHDL: GHDL checks and simulates it and converts it for synthesis and layout.

How VHDL projects run#

  1. 1
    Lint and convert
    Designs can be written in VHDL (.vhd). GHDL checks the VHDL in the lint step and converts the design to Verilog (generated/vhdl/).
  2. 2
    Build
    Synthesis, layout, and the FPGA build use the converted Verilog.
  3. 3
    Simulate
    VHDL testbenches run in GHDL. A SystemVerilog testbench can test a VHDL design too.

VHDL testbenches#

A VHDL testbench reports its result with a report statement:

vhdl
report "SF_RESULT PASS";

End the testbench with std.env.finish;. Tapeo stops the simulation at SF_RESULT PASS anyway, so a clock that keeps running does not hold the run up, but a testbench that never reports a result runs until the 3-minute limit. A waveform over 16 MiB is not kept; the result still counts.

Not supported yet#

Limits

A design that mixes VHDL and Verilog files is not supported yet. A workflow on such a project stops and lists the files of each language; remove one side and run it again. Tapeo Hub blocks are Verilog, so they are not offered or added for a VHDL design.