Design features

Tapeo Hub

Verified blocks to build with (UART, FIFO, SPI controller, PWM, debouncer). The AI suggests the ones that fit and asks before using them.

Tapeo Hub holds reusable pieces of hardware (the industry calls them IP cores, from intellectual property). The first ones are written and verified by Tapeo. Each has a public page with its parameters, ports, an example to paste, and its source: browse Tapeo Hub.

The blocks#

Block	What it does	Size
UART transmitter `uart_tx`	Sends bytes on a serial line, 8N1, at a baud rate set by CLKS_PER_BIT.	124 cells
UART receiver `uart_rx`	Receives 8N1 bytes from a serial line, with a synchronizer and framing-error detection.	187 cells
Synchronous FIFO `sync_fifo`	First-in first-out buffer on one clock, with full, empty, and a fill count.	353 cells
SPI controller `spi_master`	Exchanges bytes with an SPI peripheral in mode 0, most significant bit first.	82 cells
PWM generator `pwm`	Pulse-width modulation for LEDs, motors, and buzzers, with a WIDTH-bit duty cycle.	67 cells
Button debouncer `debounce`	Turns a bouncing button or switch into a clean signal with press and release pulses.	97 cells
Embedded logic analyzer `logic_analyzer`	Records internal signals on the FPGA around a trigger and sends the capture over its own UART; tapeo fpga capture saves it as a VCD.	5164 cells

The AI asks first#

1
It searches the Hub
From your description (and later, your question), Tapeo picks the blocks that could fit. The AI sees only those, so this works the same as the Hub grows.
2
It suggests and explains
The Architect's proposal or answer lists at most 5 blocks: what each one is for in your design, how it connects, and a short picture of the whole, such as button pin → debounce → control logic → pwm → LED.
3
You choose
New designs: every suggested block is ticked; untick any you do not want, or untick all to have the AI write everything. The build plan says which are used. Changes: the Architect adds them only after you agree in the chat.
4
It builds around them
The blocks are added to the project as they are, and the AI writes the rest: the top module that connects them, any logic they do not cover, and the testbench.

Terminal: tapeo new lists the suggested blocks and asks (Enter keeps them all, n none, or numbers to keep). For scripts, --hub all, --hub none, or --hub uart_tx,pwm; --yes alone keeps them all.
VS Code: Tapeo: New Design shows the blocks ticked in a list; untick any you do not want.
Architect changes: applying them (in the browser, tapeo apply, or VS Code) first adds the agreed blocks to the project and pulls them.

Note

When nothing in the Hub fits, nothing is suggested and the design is written from scratch, as before.

Limits

The blocks are SystemVerilog, and a design is built in one language. For a design in VHDL, no blocks are suggested, and adding one to a VHDL project is refused.

Add a block yourself#

In the workspace: the Tapeo Hub button in the project header. Add to project copies its RTL and a README with an instantiation example into ip/.
In VS Code: Tapeo: Add from Tapeo Hub.
From the terminal, in the project folder:

$ tapeo hub

$ tapeo hub add uart_tx

tapeo ip does the same as tapeo hub. Adding a block again does nothing while your copy is unchanged; a copy you changed is replaced only with --replace (or Replace in the workspace).

In your project#

A block lives in ip/<block>/: its RTL (<block>.sv) and a README.md with its parameters, ports, and how to instantiate it.
It is your file: you can read and change it. Blocks a new design was built with are protected from automatic AI repairs, so a failing run fixes your design around them instead of rewriting them; unlock a file to allow repairs.
A block that is added but not used yet is never chosen as the design's top module.

What verified means#

Each block is checked by Tapeo before every release: its self-checking testbench passes in Icarus Verilog, Verilator -Wall reports nothing, and Yosys synthesizes it. That shows it works for the tested cases; your own testbench checks it in your design.

Limits

Blocks published by users, and search by process, area, or license, are planned and not available yet.