Package pin map and KiCad parts

A board designer needs the chip as a schematic symbol with a footprint, and the pinout has to match the design exactly. Tapeo checks the pinout and writes the KiCad parts, using KiCad itself to read them back. Experimental.

Write the map#

Name a footprint from KiCad's standard library and give every pad a port bit, a supply, or NC in package/package.json:

{
  "name": "uart_tx_chip",
  "footprint": "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm",
  "supplies": { "VDD": "power", "VSS": "ground" },
  "pins": {
    "1": "clk", "2": "rst", "3": "start", "4": "VSS",
    "5": "data[0]", "6": "data[1]",
    "13": "NC", "14": "VDD", "15": "tx"
  }
}

• Each bit of a bus gets its own pad: data[0], not data. Use the index the RTL declares.
• A supply can be on several pads; an exposed pad has a number too (pad 17 on a 16-pin QFN).
• A misspelled footprint is answered with close names from KiCad's library.

Check it#

Press Check the pin map in the Workflow tab, or run tapeo check package (VS Code: Tapeo: Run a Check Now, then Package). It takes about 10 seconds.

1. 1
   The pads

   The footprint is read from KiCad 9's own library, so the pad numbers are the real ones (paste-only pads are not pins).
2. 2
   The ports

   Yosys reads your design's top-level ports, so the names and bus indices are the ones the design really has.
3. 3
   The map

   Every pad must be assigned, every port bit must be on exactly one pad, every supply must be on a pad, and there must be at least one power and one ground pad.
4. 4
   KiCad reads it back

   Tapeo writes the symbol (generated/package/<name>.kicad_sym) and a sheet with the chip and a global label on every pin (.kicad_sch). KiCad exports the sheet's netlist, which must put every pad on the net the map says, and draws the symbol and footprint for the panel. Click a drawing for a full view: scroll or pinch to zoom, drag to move, the arrow keys switch drawings, and Download saves the SVG.
5. 5
   Your chip, packaged

   A 3D view of the part on a patch of board, drawn from KiCad's footprint at its real size: the body, its legs (or balls, or flat pads), your chip's name, and the pin-1 dot. Hover a leg for its pad and signal; Pin names labels them all. Look inside makes the body see-through: your die, to scale, on its paddle, with a gold bond wire from each of its pins to the leg the pin map gives it. Zoom to the die flies in; Open the die in 3D opens its layout. Your die has no pad ring yet, so the wires land on its edge pins.

The Package pin map panel shows KiCad's drawings, every pad, and any problems; readiness has a Package pin map section, and tapeo package prints the same. tapeo check package exits 1 when the map is wrong.

Use it on a board#

• Pull the outputs (tapeo pull --outputs) and add generated/package/<name>.kicad_sym to your board project's symbol libraries. The footprint is KiCad's standard one, which every KiCad install has.
• Or add the generated sheet to your schematic as a sub-sheet: its global labels connect to your board's nets of the same name.
• Run KiCad's electrical rules check and design rules check on your board. Tapeo does not run them on a sheet with only the chip, where every pin is unconnected by design.

What it is not#