Sign in through your browser: check the code, approve the device, and the terminal finishes signing in. The server is https://tapeo.net unless you name another.
--token Paste a token from Account → VS Code and terminal access instead (hidden prompt).
Create an empty project and bind the folder to it.
—
tapeo delete [project-id]
Delete a project on the server for good: files, checkpoints, runs, layouts, and Architect history (a running workflow stops). It deletes this folder's project unless you name one, asks you to type the project name, and keeps your local files; the folder is no longer linked.
--yes Skip the typed confirmation (for scripts). Without a keyboard, --yes is required.
tapeo pull [project-id] [folder]
Download source files without overwriting local edits. In a bound folder, the project id can be left out.
--outputs Also download tool outputs (generated/, signoff/) read-only. Outputs over 25 MB are listed for tapeo download.
tapeo status
Local changes (modified, new, deleted, too large) and the latest run.
—
tapeo push <path...>
Save the named files in Tapeo. Each push names the version it was based on; a file changed on the server meanwhile is refused and its server copy saved in .tapeo/conflicts/.
--all Push every modified and new source file.
tapeo rm <path>
Delete a file on the server (only the version last pulled) and locally.
—
tapeo mv <from> <to>
Rename a file on the server and locally.
—
tapeo download <path> [destination]
Download one project file of any size, such as a GDS layout.
—
tapeo lock <path...>
Protect files from automatic AI repairs during runs: the Architect's fixes become suggestions you review. Files you push are protected by default.
—
tapeo unlock <path...>
Let the Architect repair these files during runs again.
—
tapeo checkpoints
Saved checkpoints (yours, the AI's, and each run's), newest first.
—
tapeo checkpoint ["name"]
Save a checkpoint of the files saved in Tapeo now (push local edits first).
—
tapeo restore <checkpoint> <path...>
Put back a file's version from a checkpoint: written locally and saved in Tapeo as your edit, like Restore in Project history.
—
tapeo target [simulation|fpga|asic|fpga-asic]
Show or change where the design runs.
--board --board <id> picks the FPGA board for fpga and fpga-asic targets.
--clock --clock <MHz> sets a design clock made by a PLL; leave it out for the board clock.
tapeo process [id]
Show or change the chip process. A change removes the old process's flows, netlists, layouts, and signoff outputs; the next run rebuilds them.
Design a new chip with the Architect: answer its questions, choose an option, check the build plan, then build. When Tapeo Hub blocks fit, it lists them (what each is for and how it connects) and asks which to use (Enter keeps them all). The generated files are pulled into the folder.
--from-files Start from the design files already in the folder (up to 20 files, 300 KB).
--option --option N chooses design option N.
--mode --mode quick | guided: Quick prototype (fewest questions, disclosed defaults) or Guided design (the default). Asked when run in a terminal.
--auto-answers Answer every question with “Not sure — you choose”.
--hub --hub all | none | <block,block> chooses the suggested Tapeo Hub blocks without asking (--yes alone keeps them all).
--yes Confirm the build (one build from your plan) without asking.
--no-build Create the project without building it.
tapeo ask "<question>"
Ask the Architect about the project. The answer streams in; proposed file changes are saved for review.
—
tapeo history
The Architect conversation, shared with the browser.
--limit --limit N shows the last N messages (default 10).
tapeo proposals
The Architect's proposed file changes, with diffs.
—
tapeo apply [n...]
Apply proposed changes to local files (all of them, or the numbered ones). Tapeo Hub blocks you agreed to in the chat are added to the project and pulled first. Push afterwards.
—
tapeo discard
Forget the proposed changes.
—
tapeo problems [run-id]
Tool errors and warnings as file:line:col (latest run by default).
Lint the pushed design RTL with Verilator in seconds (a stage run, not a build) and list its errors, warnings, and style notes as file:line. Exits with an error when lint finds errors.
—
tapeo run
Start a full run on the saved files (one build from your plan).
--stage --stage <stage> reruns one stage (not a build).
--from --from <stage> reruns that stage and every later one.
--resume Reuse stages whose content-hashed inputs, settings, tools, dependencies, and outputs are unchanged; use --from to narrow the range.
--no-ai-repairs Turn off AI repairs for a stage run.
--watch Follow the run, then show its results and goals. Exits with code 3 when the run fails.
Without a target: each shuttle's submission status (wrapper, problems, last precheck verdict, GDS and log paths). With a target: build the design with that shuttle's official template and run its official precheck (uses one build; takes one to several hours). Only a passing precheck on the current sources is reported as ready to submit.
--watch Follow the build, then show its result.
tapeo watch [run-id]
Follow a run until it ends, then show its results (the latest run by default).
—
tapeo show [run-id]
Stage results, AI changes, and tool runs of a run.
—
tapeo logs <tool-run-id>
A tool run's saved output (ids are listed by tapeo show).
—
tapeo goals [list | add | remove | edit | save]
The latest goal report. list shows the goals and how each is measured; add <key> <op> <value> [unit] adds one (op is "<=", ">=", "=", or between low..high; --note adds a note); remove <key> removes one; edit writes .tapeo/goals.json and save uploads it. The next full run plans how a new goal is measured.
--note --note "…" adds a note to a goal from goals add.
tapeo sim
Simulate the files saved in Tapeo now: no workflow run and no build. Prints the result and the testbench's measurements; exits with an error when it fails.
--coverage Also measure code coverage of the design with Verilator (line, branch, and toggle percentages, and the lines never reached); slower than a plain simulation.
--testbench --testbench <name> runs a testbench named in tapeo.json (default: "default" or the first).
tapeo manifest
What tapeo.json resolves to on the saved files: design sources in compile order, top, testbenches, defines, include folders, constraints, and any problem that stops the stages.
—
tapeo memories
The memory plan the last synthesis saved (generated/memory/plan.json): each inferred memory, the SRAM macros it maps to with the bank and slice arrangement, or the reason it stays in standard cells, the alternatives compared, and the generated wrapper's formal equivalence proof.
—
tapeo capabilities [process]
Which checks run on each process (supported, experimental, needs your inputs, or unavailable, each with its reason), with the installed corners, rule decks, macro families and their licenses, and the shuttles and the macros each allows. Without a process it also lists capabilities that are not available yet and what each needs.
—
tapeo readiness
FPGA ↔ ASIC readiness from current evidence: simulation, formal, coverage, constraints, CDC/RDC, equivalence, mappings, timing, power, freshness, and blockers. Exits with an error when blockers remain.
—
tapeo constraints
Constraint validation for each target, including every clock's provenance and unconstrained or contradictory timing intent.
—
tapeo cdc
Structural clock- and reset-domain crossing results, including reviewed waivers. This is not signoff CDC.
—
tapeo portability
How memories and arithmetic map to FPGA and ASIC resources, target-specific primitives, assumptions, and wrapper recommendations.
—
tapeo equivalence
Saved RTL-to-ASIC and RTL-to-FPGA netlist equivalence verdicts with their method, abstractions, freshness, and limitations.
—
tapeo power
The workload-based ASIC power estimate from saved switching activity, including workload, corner, annotation coverage, model, and freshness, then the routed power grid's IR drop and electromigration screen.
Run one analysis now on the saved project without using a build, then print its report. atpg generates stuck-at test patterns with Fault on the full-scan model and reports their coverage. soc generates the bus decoder, register blocks, C header, and FuseSoC core from soc/soc.json with PeakRDL and checks every register through the bus in simulation. package checks package/package.json against the KiCad footprint's pads and the design's ports and writes a KiCad symbol and schematic sheet. mutation plants bugs in the design one at a time (--count, default 20) and runs the testbench on each (--testbench picks one, Verilog or Python), then lists the bugs it missed. soc and package exit 1 when a check fails; mutation exits 1 when the testbench fails on the unchanged design.
--count --count 20: how many bugs mutation testing plants (1 to 60).
--testbench --testbench tb/test_counter.py: the testbench mutation testing runs (default: the project's).
tapeo soc
The generated SoC: its address map, the register checks through the bus, the FuseSoC core, the generated files, and what the checks do not cover.
—
tapeo package
The package pin map: the footprint, every pad's signal, problems found against the design's ports, whether KiCad's netlist matches the map, the generated KiCad files, and what is not checked.
—
tapeo hub [add <block>]
Tapeo Hub: verified blocks (UART transmitter and receiver, FIFO, SPI controller, PWM, button debouncer), each with its size and a link to its page. `add` copies a block's RTL and README into the project under ip/<block>/, pulls them, and prints how to instantiate it.
--replace With tapeo hub add, replace a copy you changed with the Tapeo Hub version.
tapeo ip [add <block>]
The same as tapeo hub.
—
tapeo docs [add <file...> | rm <path>]
Reference documents the Architect reads, under docs/: datasheets, specifications, and notes. `add` uploads .pdf, .md, or .txt files; a PDF's text is extracted on the server (docs/name.pdf.txt, page by page) and the Architect cites its pages. `rm` removes a document (a PDF with its text). Each question gets only the passages that match it.
—
tapeo sims
Recent simulations, with the ones that saved a waveform.
—
tapeo wave [sim-id]
Save a simulation's waveform (VCD) under .tapeo/waveforms/ (the latest by default).
--out --out <file> saves it somewhere else.
--open Open it in Surfer or GTKWave when installed.
tapeo cancel [run-id]
Cancel a queued or running workflow. It stops before its next stage.
For GitHub Actions and other CI: save the checkout's files to the project (the repository is the original, so its files replace the project's, and files a person added in Tapeo that the repository no longer has are removed; files the tools and the AI made are kept), run lint → simulation with AI repairs off, and report. Any stage range, even every stage (--to lvs), is a stage run and never uses one of your plan's builds. On GitHub Actions it writes the job summary and puts each problem on its file and line. Exit code 1 when a stage fails. `tapeo ci init` writes .github/workflows/tapeo.yml.
--to --to <stage> runs from lint to that stage (--to lvs runs every stage).
--project --project <id> names the project; otherwise TAPEO_PROJECT, then the folder's binding.
--strict Also fail when a stage reports issues (for example lint warnings).
--goals Also fail when a goal is not met.
--keep-server-files Do not remove project files that the repository does not have.
--force With tapeo ci init, replace an existing .github/workflows/tapeo.yml.
Board work from your computer. devices lists programmers and serial ports; flash programs the board (as tapeo flash) and reads it back where the board allows; verify runs a hardware-in-the-loop test (program, then send and expect lines over serial, as hil/<test>.json says) and saves the result with the project, labelled board or simulated; results lists saved results and whether the bitstream changed since; monitor is tapeo monitor; capture receives one Tapeo Hub logic analyzer capture over serial and saves it as a VCD. devices, monitor, and capture need no sign-in.
--programmer --programmer openfpgaloader|fake: the real programmer (default), or a fake one that programs nothing and records what it was given (for CI). TAPEO_FPGA_PROVIDER sets the default.
--serial --serial tty|virtual|pty: a real USB serial port (default), an in-process scripted device, or a scripted device on a pseudo-terminal (the real port code runs; macOS and Linux, python3). TAPEO_SERIAL_PROVIDER sets the default. Results from fake, virtual, or pty always say simulated.
--device --device <file.json> gives the virtual or pty link a scripted device ({ banner, bannerHex, responses: [{ match, reply }], echo }); a test file's own "device" is used otherwise.
--no-program verify: test the board as it is, without programming it (the result then says the bitstream is not known).
--no-upload verify: print the result without saving it with the project.
--signals capture: the probe's signals, most significant first as in the probe concatenation, for example state:3,valid,ready,data:3.
--timeout capture: seconds to wait for a capture (default 60).
tapeo monitor
Show the connected board's serial (UART) output and send the lines you type. macOS and Linux; needs no sign-in. On Windows, use the Serial monitor on the Workflow tab in Chrome or Edge.
--port --port <path> names the serial port when there are several (a Tang Nano shows two; the serial link is usually the second).