Design features

Project files and exports

Where project files live, bringing a repository with its own layout (tapeo.json), and what you can download.

The project tree#

Project files live in a virtual project tree and are stored with their project. Generated flows and results use project-relative folders such as rtl/, tb/, analysis/, generated/, and signoff/. Exact paths depend on the project and flow; the workspace's Where should files go? guide lists the paths each workflow reads.

Path	What it is
`tapeo.json`	Optional: sources, top, testbenches, constraints, blocks, and resets.
`analysis/physical_settings.json`	Settings of the standard physical flow; `analysis/openroad_flow.tcl` is generated from them.
`analysis/memory_settings.json`	SRAM macro mapping: off, keep named memories in registers, or restrict the macros.
`constraints/cdc_waivers.json`	Reviewed clock-domain-crossing waivers, each with a reason.
`generated/`	Tool outputs: `netlists/`, `reports/` (saved checks), `memory/` (the memory plan), `blocks/` (hardened blocks), and layouts. Written by tools, not by hand.
`signoff/`	Layout-extracted netlists (`layout_extracted/`) and LVS references (`reference/`); DRC, timing, and structural reports are under `generated/signoff/`.
`docs/`	Reference documents the Architect reads.
`ip/`	Tapeo Hub blocks added to the project.
`fpga/<board>/board_top.sv`	The board wrapper for an FPGA build.

Note

Files generated by a tool or AI are kept visible as project artifacts. Review generated constraints, flow scripts, mapped netlists, and reports before relying on them for a design decision.

Your own layout: tapeo.json#

By default Tapeo treats every Verilog/SystemVerilog file outside testbench folders as the design and finds the top module and testbench itself. Bringing a repository with its own layout? Add tapeo.json at the project root to say instead:

Field	Meaning
`top`	The design's top module.
`sources`	Patterns such as `hw/*/.sv`, with `!` to leave files out.
`filelist`	A file list (`.f`), instead of or with sources.
`includeDirs`	Include folders.
`defines`	Macros.
`verification`	Shared verification files.
`testbenches`	Named testbenches.
`constraints`	The timing constraints file.
`blocks`	Modules hardened on their own and placed as macros by the top (SkyWater 130; up to two levels).
`resets`	Reset signals: which is active low or high, asynchronous or synchronous, and to which clocks, for the reset-domain checks.

json

{
  "top": "soc_top",
  "filelist": "hw/files.f",
  "sources": ["hw/extra/**/*.sv", "!hw/legacy/**"],
  "includeDirs": ["hw/include"],
  "defines": ["WIDTH=32"],
  "verification": ["verif/common/**/*.sv"],
  "testbenches": { "default": "verif/tb_soc.sv", "uart": { "files": ["verif/uart/*.sv"], "top": "tb_uart" } },
  "constraints": "constraints/soc.sdc"
}

Lint, simulation, synthesis, the FPGA build, and timing then all use it.
Workflow shows what it resolved to, and a mistake in it stops the stages with a message saying what to fix.
Without the file nothing changes.

Exports#

Project ZIP

Downloads the project files so they can be inspected or continued outside the app.

Engineering handoff ZIP

Available from Workflow when the export can be built. It packages current project files and saved evidence for engineering review; it is not automatically a foundry submission package.

See also VS Code and terminal to work on the same files locally.