Tapeo Hub
Verified blocks, ready to build with.
Reusable pieces of hardware (often called IP cores) that Tapeo wrote and checks before every release: a self-checking testbench passes, Verilator lint is clean, and Yosys synthesizes it.
- The AI asks firstWhen a block fits your design, the Architect suggests it and explains how it connects. You choose.
- Added as your filesA block goes in ip/<block>/ with a README. You can read and change it.
- Anywhere you workThe workspace's Tapeo Hub button, tapeo hub add, or VS Code.
- CommunicationUART transmitteruart_txSends bytes on a serial line, 8N1, at a baud rate set by CLKS_PER_BIT.Verified by Tapeo124 cellsUARTserial outputDetails →
- CommunicationUART receiveruart_rxReceives 8N1 bytes from a serial line, with a synchronizer and framing-error detection.Verified by Tapeo187 cellsUARTserial inputDetails →
- MemorySynchronous FIFOsync_fifoFirst-in first-out buffer on one clock, with full, empty, and a fill count.Verified by Tapeo353 cellsFIFObufferDetails →
- CommunicationSPI controllerspi_masterExchanges bytes with an SPI peripheral in mode 0, most significant bit first.Verified by Tapeo82 cellsSPIDetails →
- Timing and controlPWM generatorpwmPulse-width modulation for LEDs, motors, and buzzers, with a WIDTH-bit duty cycle.Verified by Tapeo67 cellsPWMDetails →
- InputButton debouncerdebounceTurns a bouncing button or switch into a clean signal with press and release pulses.Verified by Tapeo97 cellsbutton inputswitch inputDetails →
- DebugEmbedded logic analyzerlogic_analyzerRecords internal signals on the FPGA around a trigger and sends the capture over its own UART; tapeo fpga capture saves it as a VCD.Verified by Tapeo5164 cellslogic analyzerdebug captureUARTDetails →
More blocks will follow, and later blocks published by users. How it works: Tapeo Hub in the docs.