FPGA boards

Where it runs#

• When you describe a design, the Architect asks where it should run: simulation only, an FPGA board, a chip, or an FPGA board and a chip.
• You can change it later under Where it runs on the Workflow tab.
• For a board, the project uses the same RTL, testbench, and simulation, then builds a bitstream for that board.
• With a chip as well, the bitstream comes first and the chip stages follow.

Boards#

• Their LEDs, buttons, switches, UART, and PMOD or GPIO pins come from the board makers' own pin files; the AI never chooses pins.
• Pick the ULX3S size printed on its FPGA.

Board wrapper and clock#

• A small file, fpga/<board>/board_top.sv, connects your design to the board's signals. The AI writes it and you can review it; Tapeo checks its ports and generates the pin constraints in generated/fpga/<board>/. Simulation and chip synthesis leave this file out.
• Design clock: leave it empty to use the board's clock, or set another frequency within the board's PLL range. Tapeo then generates a tapeo_pll module with the toolchain's own PLL calculator, and timing is checked at the frequency it really makes (for example 50.143 MHz when you ask for 50 on a Tang Nano 9K).

Build and results#

After simulation passes, Yosys and nextpnr build the design for the board in an isolated runner. The Workflow tab shows the build in one line (built or not, logic used, Fmax against the clock) with Open Board tab. The Board tab shows how much of the FPGA it uses, its maximum clock speed (Fmax) against the design clock, the pins in use, a board view of the parts the design uses, and a Download bitstream button. These numbers can be measured goals.

Program the board#

Connect the board by USB, then in the project folder:

$ tapeo flash

# keep the design after power-off$ tapeo flash --flash

• Or use Tapeo: Program FPGA Board in VS Code.
• It downloads the bitstream and runs openFPGALoader on your computer (install it first).
• Tapeo's servers never access your USB devices.

Serial monitor#

See what the design prints on its UART, and type lines to send to the board:

• The Serial monitor on the Board tab (Chrome or Edge on a computer; your browser asks which port).
• In a terminal (macOS and Linux):
• Tapeo: Open Serial Monitor in VS Code (macOS and Linux).

$ tapeo monitor

Hardware tests#

Write a test that talks to the design over serial, then run it on the board. A test is a JSON file in the project, for example hil/smoke.json:

{
  "steps": [
    { "expect": "READY", "timeoutMs": 3000 },
    { "send": "status
" },
    { "expect": "LED=(\d)" }
  ]
}

$ tapeo fpga verify hil/smoke.json

• It programs the board, runs each step, and saves the result with the project. See them in the Hardware tests section on the Board tab, with tapeo fpga results, or Tapeo: Show Hardware Test Results; Tapeo: Run Hardware Test runs one from VS Code.
• Every result says what produced it: Real board (openFPGALoader and a real serial port), Board, bitstream not checked (--no-program), or Simulated, no board (the fake programmer or a virtual or pseudo-terminal device, for CI and for trying a test). Only a current real-board result counts in readiness.
• A result goes stale when the bitstream is rebuilt.
• A passing test shows what that test checks on that board. It is not full board validation.

Logic analyzer#

Add the logic_analyzer block from Tapeo Hub to record internal signals on the FPGA around a trigger. It sends the capture over its own UART; save it as a waveform:

$ tapeo hub add logic_analyzer# after the board has captured:$ tapeo fpga capture --signals state:3,valid,ready,data:3 --clock 27 --out capture.vcd

• --signals names the probe's fields, most significant first, as in the probe concatenation; --clock is the design clock in MHz.
• Or use Tapeo: Capture from Logic Analyzer in VS Code. The capture is checked with its checksum before it is saved.

Limits for now#