Tapeo

Design features

Physical design and layout

Layout views in 2D and 3D, the physical summary, signal replay, and the checks Tapeo adds around your OpenROAD flow.

Layout views#

  • The Logic view can show a rendered view of an exported GDS layout when the project has one and the layout renderer is available. This is a visual aid for inspecting geometry, not an interactive chip editor or a manufacturing approval.
  • The layout viewer supports 2D inspection and an illustrative 3D layer stack. Fullscreen, fit and zoom controls, box zoom, layer visibility, cell/net selection, and saved-run comparison help inspect the exported geometry.
  • Use 2D for precise geometry inspection and 3D to understand layer order and routed connectivity.
  • After a shuttle build, the picker above the layout switches between the design layout (Tapeo's flow, with Tapeo's checks) and the shuttle submission (your design inside the shuttle's frame, built by the shuttle's own tools: the file you submit, with its precheck verdict). View layout in the Shuttle submission panel or on a GDS file opens it.

The 3D view

  • It opens on the whole chip with every wiring layer at its process height (SkyWater 130 nm and IHP SG13G2; heights are approximate and drawn taller than real).
  • Standard cells appear as blocks colored by kind, and macros such as an SRAM as labeled blocks.
  • Double-click anywhere, or choose a region or macro in the 3D controls, to load every layer of that area, including transistor layers.
  • The layer list shows how many shapes are drawn on each layer. Regions are inferred from where cells were placed, not from RTL modules.
  • A layout opens in seconds after its first view.

Moving around

  • Drag moves the chip; right-drag (or Shift+drag) tilts and turns it; scroll or pinch zooms towards the pointer. On a trackpad, two-finger scrolling moves the view once Tapeo sees a sideways scroll (switch it with Trackpad on the pad).
  • The pad in the bottom-right corner has move arrows, Fit chip (⤢), zoom, turn by 45°, a Tilt slider from straight down (0°) to almost side-on (85°), the views Top, Front, Side, and 3D, and Fit selection for a traced route or loaded area. Its mini-map outlines what you are looking at; click it to go there. The compass shows which way is north; click it to straighten up.
  • Keys (click the view first): arrows or W A S D move, + − zoom, Q E turn, R F tilt, 0 fits the chip, T is the top view, L separates the layers, ? lists them. On phones and tablets one finger moves, pinch zooms, and two fingers turn and tilt.

Your code on the chip

Show my code colours every cell by the part of your design it came from, with a list of your modules and the share of the chip each one takes (“counter (u_count) · 28 cells · 58% of your design’s area”). Click a module to highlight it and fly to it, or click a cell to see where it came from and open it in Code. Flip-flops know their exact line (“Flip-flop holding q[3] · counter.sv line 5”); logic gates lose their line when synthesis optimises them, so they are placed with the module they feed. Grey cells were added by the layout tools (fillers, taps, buffers). It needs a synthesis and layout run from after this feature; older layouts say so.

Finding problems

  • Slow path: the slowest signal path drawn as a glowing line from where it starts to where it arrives, through each cell, with how long it takes, how long it may take, the time to spare (slack), and the cells that cost the most time, in your modules. It needs a layout run from after this feature.
  • Rule checks: each place that breaks a factory rule (from the DRC run and the router's own check) as a red marker, listed in plain words (“Two shapes on met1 are closer together than the factory allows”); click one to fly to it.
  • Crowding: where the routed wiring is densest, from blue to red, compared with the busiest area of the same chip. It does not measure routing capacity.

Separate layers

A chip is built like a building: the transistors and cells on the ground floor, the wiring on the floors above, short wires low and long wires (and the power grid) high. Separate layers pulls the floors apart, labels each one in plain words, and lists them; click a floor to look at it alone. Join layers puts them back. A traced route hides while the layers are apart.

Physical summary#

The physical design summary reports values when they can be extracted from saved tool runs: placement/routing state, die and core dimensions, utilization, placed instances, estimated or measured wire length, vias, and DRC results.

Note

Some fields may say “not reported” because a particular flow does not emit that measurement. The UI does not fill those gaps with guesses.

Signal replay#

When a saved simulation waveform and DEF routes are available, the 3D view can replay a selected signal against a selected routed net. It shows the VCD value and time, and labels the signal-to-net match as exact, inferred from a bus range, manually selected, or unmatched.

Limits

The moving marker illustrates timeline position on the route; it does not model propagation or delay, and the VCD and route are not a timing-aware co-simulation. A manual pairing is not proof of electrical connectivity.

Automatic steps and checks#

Automatic physical-design steps

Around your project's OpenROAD flow, Tapeo adds platform-declared steps the flow does not already perform:

  • RTL ports that only feed hard-macro supply pins (for example an SRAM's vdd/vss) are tied to the platform supply nets.
  • If the flow never builds a power grid, the platform power-grid recipe is generated before placement.
  • Platform well taps are inserted, which also stops standard-cell rows and power rails from running across hard macros.
  • Process-pack macro power stripes are added, and each output port gets its own buffer so no two ports share a net.
  • After routing, antenna diodes are inserted and the design is rerouted, filler cells are placed, and every standard cell and macro is checked for a connection to the power grid.

The run summary and inputs list each step that was applied.

SkyWater standard flow and checks

On SkyWater HD and HS, the physical run can use a generated OpenROAD flow with bounded settings for die size, macro spacing, placement and routing. It reconnects supply pins after clock-tree and timing repair, then checks mapped-to-routed logic equivalence. Process-pack slow and fast Liberty files enable exploratory post-route timing at several corners; when the pack has min and max RC rules too, slow corners use the max RC extraction and fast corners the min. Design rules are checked twice: KLayout with the full SKY130 deck the shuttle prechecks use (front-end, metal, and off-grid rules), and Magic's full DRC, which runs in the DRC stage on its own. Your own testbench then runs against the routed netlist with the process cell models (gate-level simulation); a testbench that reads internal RTL signals is skipped. To tune the layout, change analysis/physical_settings.json or ask the Architect; the generated analysis/openroad_flow.tcl is rebuilt from it on every run. A failed or incomplete check stays visible; these results do not certify foundry signoff.

Power grid: IR drop and electromigration

With the standard flow (SkyWater 130 HD and HS, GF180), each layout run also checks the routed power grid. OpenROAD PDNSim works out the static voltage drop on the power and ground nets, using the Liberty's own supply voltage. It also works out the current in every grid wire, and Tapeo compares that current with the layer's limit in the process tech LEF. A wire over its limit fails readiness. Vias are compared with a single cut's limit, which is only an upper bound. Voltage drop is shown but not judged. tapeo power prints the report per net and layer. Not covered: signal wires, RMS or peak limits, temperature derating, currents from your simulation, dynamic drop, and the package. Signal integrity (crosstalk) and thermal analysis are not available.

Shuttle submission

Tapeo's own layout is for exploring and checking the design. To manufacture it, build it with a shuttle's official template and precheck: see Shuttle submission.

Hard-macro power connections

For explicitly instantiated hard macros, the selected process pack may declare verified power-grid via stacks from the macro LEF supply-pin layers to a named platform PDN grid. Tapeo inserts those connections before OpenROAD generates the grid; it does not infer metal layers or reuse another process setup.

Antenna and electrical-rule checks

  • After detailed routing, OpenROAD repairs antenna violations with the library's antenna diodes when the selected platform LEFs include antenna rules, then checks them; net and pin violation counts are recorded separately, and a missing count stays unknown.
  • CVC-RV ERC runs after Magic extraction when the selected process pack supplies a driver, configuration, device models, and supply definitions; Tapeo adds which nets are driven from outside the layout (top-level inputs and black-boxed hard-macro outputs).
  • Missing collateral is shown as skipped rather than a pass. Both checks save their measured result and tool evidence in the workflow.

LVS reference and DRC attribution

  • LVS compares the extracted layout with the netlist OpenROAD actually implemented for that same layout run, because physical design adds tie cells, antenna diodes, and supply connections that an RTL re-synthesis cannot contain.
  • Hard-macro supply pins stay in the comparison, so an unpowered macro fails LVS.
  • DRC results are split into violations in your routed design, inside declared hard macros (the IP's own geometry), and inside other library cells, with a per-rule summary file.
  • Signoff readiness shows the design-rule check with one line per tool (KLayout and Magic), the shuttle's own precheck when one has run (and whether your sources changed since), and the constraints timing used. An SDC the AI wrote stays exploratory until you edit it or choose Confirm constraints.

Optional static power-grid check

  1. 1
    Route the design
    After a current OpenROAD route, select the Workflow map's Power-grid integrity stage.
  2. 2
    Run the grid check
    It requires a process-matched power grid: a platform PDN recipe that the OpenROAD flow sources before pdngen (SkyWater 130, IHP), or the grid the standard flow builds itself (GF180), built before routing.
  3. 3
    Read the results
    The stage shows worst-case and average IR drop and worst-case voltage under Outputs and measurements; native voltage/current data is saved under generated/signoff/.

The current FULL source model assumes an ideal supply at the top metal layer. It does not model package bumps or straps or establish signoff. Workload-based ASIC power is a separate OpenSTA estimate from saved simulation activity and reports its annotation coverage. Platforms without their own configured PDN recipe cannot run the grid check.

Readiness, reports, and safe resume

The readiness panel brings simulation, constraints, CDC/RDC, portability, equivalence, timing, power, DRC, and LVS evidence together for FPGA and ASIC targets. It identifies stale or missing evidence and links blockers to their reports. Each run also records stage inputs, settings, tools, dependencies, and output hashes. A resumed scoped run reuses only an unchanged stage with intact outputs; otherwise that stage runs again.

Workflow run reports

Each run records every stage with its status and full message. The run summary lists them with counts of completed, needs-review, failed, and skipped stages, and a filter to show only stages that need attention. A stage that ran but measured findings, such as DRC violations or an LVS mismatch, is marked “Needs review” rather than shown as a clean completion.

Manufacturing test#

A chip is tested after manufacture by loading patterns through scan chains and checking what comes out. Tapeo can insert the chains and generate the patterns.

  • Scan chains: set scan_chains in analysis/physical_settings.json to 1 or more. OpenROAD then replaces the flip-flops with scan flip-flops and stitches them into chains ordered by placement, adding scan_enable, scan_in_<n>, and scan_out_<n> ports. Timing, equivalence, and gate-level simulation check the chip in normal operation (scan_enable held at 0). SkyWater 130 HD and GF180; not yet SkyWater 130 HS.
  • Test patterns (ATPG): tapeo check atpg, the readiness panel's button, or Tapeo: Run a Check Now in VS Code. Fault with its Quaigh engine generates stuck-at patterns for the mapped netlist and reports their coverage twice: on its gate model and re-simulated on the process cells.
  • Readiness shows the result as issues until the layout has the scan chains the patterns assume.

Limits

Stuck-at faults only, on a full-scan model. Not covered: transition and path-delay faults, cell-internal defects, tester file formats, or test time. Designs with SRAM macros or hardened blocks are not run. This is not a production test program.

Files and sync#

Files stay in sync with workflow runs

  • The Files panel has a Refresh button and also reloads automatically when a workflow run finishes or when you return to the tab.
  • Files a run changed get a teal dot until you open them.
  • Autosave only sends files you edited and tells the server which version you started from, so an older tab can no longer overwrite a newer workflow result.
  • If a file you edited also changed on the server, it is marked as a conflict and you choose to keep your version or use the server's.

Very large files

Files over 8 MB, such as the SKY130 HS Liberty library or a large routed DEF, are not loaded into the editor. Opening one shows its size and a download button. Tools, workflow runs, and the Layout view still read the full file from project storage.

What the views are not#

Limits

Neither view replaces DRC/LVS, timing or power analysis, process-qualified signoff, or foundry approval. Cell/net selection does not provide a guaranteed trace back to RTL hierarchy.