Tapeo
Beginner-friendly · Nothing to install · Real tools

Your first chip, without the toolchain headache.

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Real tools underneath

  • Yosys
  • OpenROAD
  • OpenSTA
  • KLayout
  • Magic
  • Netgen
  • Icarus Verilog
  • RISC-V GCC

Process platforms: SKY130 HD/HS · GF180MCU · IHP SG13G2 · Nangate45

Scroll through the foundry

01 / INTENT

Describe the machine

Start with behavior, interfaces, constraints, and the job the hardware must perform.

artifact://requirements.json
AI Architect · requirements review
Keep scrolling
New · available now

Tapeo
Hub.

Don’t start from zero. Build with hardware blocks that are already verified, and let the AI glue them into your design.

  • 01
    Verified by Tapeo

    UART transmitter and receiver, FIFO, SPI controller, PWM, and debouncer. Each testbench passes, lint is clean, and it synthesizes, checked before every release.

  • 02
    The AI asks first

    When a block fits, the Architect suggests it, explains how it connects to the rest, and uses it only if you agree. It writes everything else.

  • 03
    Yours to change

    A block is added to your project with a README: parameters, ports, and how to instantiate it.

Coming next · on the roadmap
  • Blocks published by users
  • Search by process, area, and license
  • Whole projects as baselines
  • Compose systems on a bus
YOUR_DESIGN.TOPSKY130 HD
Your design
the AI writes it
Sync FIFO
sync_fifo
UART TX
uart_tx
UART RX
uart_rx
SPI
spi_master
PWM
pwm
Debouncer
clean button input
GLUE LOGIC · WRITTEN FOR YOUR DESIGN

Illustration. Every block shown is a real Tapeo Hub block.

New · FPGA Lab

One design.
Your choice of destination.

Describe it once. The same RTL, testbench, and goals can stop at simulation, go to silicon, or run on an FPGA board on your desk.

YOUR DESIGN
RTL + tests
+ goals
  • Simulate
    Available nowSelf-checking testbench · Waveforms · Goals checked
  • FPGA
    New · previewBoard + pin mapping · Fmax and utilization · Bitstream, then run it
  • ASIC
    Available nowSynthesis and timing · Place & route, GDS · DRC, LVS, ERC

From verified RTL
to a board in your hand.

  1. 01
    Pick a board

    Sipeed Tang Nano 9K and 20K, 1BitSquared iCEBreaker, or Radiona ULX3S. The Architect recommends one that fits your design’s logic, memory, clock, and I/O, with pins from the makers’ own files, never guessed.

  2. 02
    Map it to the real world

    Ports become buttons, LEDs, switches, UART, and PMOD or GPIO pins. A reviewable board wrapper and pin constraints are generated for you, and a PLL when your design needs its own clock.

  3. 03
    Build with evidence

    Yosys and nextpnr, with Apicula (Gowin), IceStorm (iCE40), and Project Trellis (ECP5), report utilization, Fmax against your clock, pins, and logs, checked as goals.

  4. 04
    Run it for real

    Program the board from your terminal or VS Code with tapeo flash, and watch its UART output live in your browser or with tapeo monitor.

FABRIC · PLACE & ROUTEnextpnr
BITSTREAM.BIN ↓
FPGA
LED[7:0]counter
uart › hello from your FPGA

Available now as a preview. The fabric, board, and bars are illustrations, not measurements.

New · work where you code

The same project.
Your favorite workspace.

Work on ordinary files in your own editor or shell. The VS Code extension and the tapeo command connect to the same Tapeo projects and server-run workflow: design with the Architect, push your files, run the workflow, see tool errors on the line that caused them, and ask the Architect for a fix you review and apply.

Illustration, played as an animation: a design file is edited in VS Code, pushed and run with the tapeo command; a syntax error appears on its line in the editor and in tapeo problems; the Architect proposes a one-line fix that is applied; the next run passes every stage and all goals.

Animated illustration of the real commands. Install the terminal client with npm install -g tapeo-cli; the VS Code extension is “Tapeo” in the Extensions view. Both sign in through your browser. Layout views and the Goals editor are in the web workspace.