← All examples

Simple synchronous watchdog · Example, read-only. Explore every file, run, and layout.

A synchronous watchdog timer that raises an alarm when it is not serviced in time, with every goal verified.

Make my own copyFree account · uses no trial credits
Custom ASIC / SoC · Simple synchronous watchdogPersisted
Custom ASIC / SoC · Simple synchronous watchdog
Project ID f6b6db69-1537-4851-92b1-0f7d6ab0f807
Files
The HDL is the source of truth. AI suggestions are reviewable before they touch the project.
Tapeo · flow mapReady to run

How your design is built

Each stage shows the files it used and produced, and who made them. Select a stage to open or protect its files, then rerun just that stage or everything after it. Whether your goals are met is in Evaluation.

6 steps with evidence2 skipped / unavailable17 expected outputs missing2 RTL files1 testbenches0 mapped artifactsLatest goal report29 passed
Manufacturing process

AI recommendation: SkyWater 130 nm · HS. You can change the platform and rerun; each platform uses its own libraries and physical-design setup.

Workflow run history

0 saved runs, newest first.

No saved workflow runs yet.

End-to-end development map

Follow the design, files, and evidence through every tool

Branches show retries and optional checks. Select a step to inspect its recorded inputs, outputs, and tool logs below. Pan and zoom to explore the map.

Run status · latest saved evidence
RunningPassedCompletedFailedBlockedStale evidenceReady to runSkippedNot run yetNot integrated / installedExpected file missing
Selected stage · 01

RTL simulation

Icarus Verilog

A testbench is present. Run it to establish behavioral evidence.

Inputs used
Who made it · lock = protected from AI repairs
  • AI
  • Tool
  • AI
Outputs and measurements

No output or measurement recorded yet.

Verification layer

Goals and test evidence

29 passed29 checked
reset_clears_stateBehavior: Synchronous reset clears the active output, timeout output, and countdown state resultpassed

reset_clears_state = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
reset_clears_state = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
start_loads_timeoutBehavior: A start request loads the programmed timeout value and asserts active resultpassed

start_loads_timeout = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
start_loads_timeout = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
countdown_progressesBehavior: A running watchdog decrements once per clock while no start or kick request is asserted resultpassed

countdown_progresses = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
countdown_progresses = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
kick_reloads_without_timeoutBehavior: A kick while active reloads the programmed timeout and does not assert timeout resultpassed

kick_reloads_without_timeout = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
kick_reloads_without_timeout = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
repeated_kicks_prevent_timeoutBehavior: Repeated kicks keep the watchdog active and prevent timeout while kicks continue resultpassed

repeated_kicks_prevent_timeout = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
repeated_kicks_prevent_timeout = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
timeout_pulse_asserts_at_expirationBehavior: The watchdog asserts timeout when the terminal countdown condition is reached resultpassed

timeout_pulse_asserts_at_expiration = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
timeout_pulse_asserts_at_expiration = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
timeout_pulse_one_cycleBehavior: Timeout is asserted for exactly one clock cycle and is low otherwise resultpassed

timeout_pulse_one_cycle = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
timeout_pulse_one_cycle = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
active_stops_after_timeoutBehavior: Active deasserts after timeout and remains deasserted until a new start resultpassed

active_stops_after_timeout = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
active_stops_after_timeout = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
restart_after_timeoutBehavior: A new start after timeout reloads the watchdog and restarts active operation resultpassed

restart_after_timeout = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
restart_after_timeout = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
kick_priority_at_terminal_countBehavior: Kick takes priority over timeout when both coincide at the terminal countdown condition resultpassed

kick_priority_at_terminal_count = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
kick_priority_at_terminal_count = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
zero_timeout_expires_on_first_counting_edgeBehavior: A programmed timeout value of zero remains active after start and emits one timeout pulse on the first subsequent counting edge resultpassed

zero_timeout_expires_on_first_counting_edge = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
zero_timeout_expires_on_first_counting_edge = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
start_priority_over_running_stateBehavior: Start takes priority over the existing running countdown and reloads the programmed value resultpassed

start_priority_over_running_state = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
start_priority_over_running_state = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
reset_aborts_active_watchdogBehavior: Synchronous reset aborts an active watchdog and clears timeout on the reset edge resultpassed

reset_aborts_active_watchdog = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
reset_aborts_active_watchdog = 1 result; met the goal target.
Used: rtl/watchdog.sv · tb/testbench.sv
setup_slack≥ 0 nspassed

setup_slack = 18.065699 ns; goal passed.

Measured 18.065699 ns · OpenSTA
OpenSTA · passed
setup_slack = 18.065699 ns; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/opensta_timing.tcl
global_route_overflow≤ 0 edgespassed

global_route_overflow = 0 edges; goal passed.

Measured 0 edges · OpenROAD
OpenROAD · passed
global_route_overflow = 0 edges; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
antenna_violation_count≤ 0 violationspassed

antenna_violation_count = 0 violations; goal passed.

Measured 0 violations · OpenROAD
OpenROAD · passed
antenna_violation_count = 0 violations; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
antenna_net_violation_count≤ 0 netspassed

antenna_net_violation_count = 0 nets; goal passed.

Measured 0 nets · OpenROAD
OpenROAD · passed
antenna_net_violation_count = 0 nets; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
antenna_pin_violation_count≤ 0 pinspassed

antenna_pin_violation_count = 0 pins; goal passed.

Measured 0 pins · OpenROAD
OpenROAD · passed
antenna_pin_violation_count = 0 pins; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
antenna_check_complete= 1 resultpassed

antenna_check_complete = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
antenna_check_complete = 1 result; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
power_grid_vdd_unconnected_instances≤ 0 instancespassed

power_grid_vdd_unconnected_instances = 0 instances; goal passed.

Measured 0 instances · OpenROAD
OpenROAD · passed
power_grid_vdd_unconnected_instances = 0 instances; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
power_grid_vss_unconnected_instances≤ 0 instancespassed

power_grid_vss_unconnected_instances = 0 instances; goal passed.

Measured 0 instances · OpenROAD
OpenROAD · passed
power_grid_vss_unconnected_instances = 0 instances; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
power_grid_vdd_connected= 1 resultpassed

power_grid_vdd_connected = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
power_grid_vdd_connected = 1 result; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
power_grid_vss_connected= 1 resultpassed

power_grid_vss_connected = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
power_grid_vss_connected = 1 result; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
layout_export_complete= 1 resultpassed

layout_export_complete = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
layout_export_complete = 1 result; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
parasitic_extraction_complete= 1 resultpassed

parasitic_extraction_complete = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
parasitic_extraction_complete = 1 result; met the goal target.
Used: generated/netlists/watchdog.mapped.v · generated/libraries/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib · constraints/watchdog.sdc · analysis/openroad_flow.tcl
layout_extraction_complete= 1 resultpassed

layout_extraction_complete = 1 result; goal passed.

Measured 1 result · Magic layout extraction
Magic VLSI · passed
layout_extraction_complete = 1 result; met the goal target.
Used: generated/layout/watchdog.openroad.gds
erc_violation_count≤ 0 violationspassed

erc_violation_count = 0 violations; goal passed.

Measured 0 violations · CVC-RV
CVC-RV · passed
erc_violation_count = 0 violations; met the goal target.
Used: signoff/layout_extracted/watchdog.spice
erc_check_complete= 1 resultpassed

erc_check_complete = 1 result; goal passed.

Measured 1 result · CVC-RV
CVC-RV · passed
erc_check_complete = 1 result; met the goal target.
Used: signoff/layout_extracted/watchdog.spice
lvs_match= 1 resultpassed

lvs_match = 1 result; goal passed.

Measured 1 result · Netgen LVS
Netgen LVS · passed
lvs_match = 1 result; met the goal target.
Used: signoff/layout_extracted/watchdog.spice · signoff/reference/watchdog.post-route.v
Loading tool and run history…Available stages run automatically when their inputs and enabled tools are ready. Physical implementation and fabrication signoff still require project-specific flows and tools.
Simulation
Run the testbench to compile and simulate the current HDL project.