Turn intent into
verified silicon.
Secure design workspace
Welcome back
Sign in to continue working on your hardware projects.
Real tools underneath
- Yosys
- OpenROAD
- OpenSTA
- KLayout
- Magic
- Netgen
- Icarus Verilog
- RISC-V GCC
Process platforms: SKY130 HD/HS · GF180MCU · IHP SG13G2 · Nangate45
Scroll through the foundry
Describe the machine
Start with behavior, interfaces, constraints, and the job the hardware must perform.
The Tapeo
Marketplace.
Don’t start from zero. Reuse hardware the community has already built and verified, and let the Architect assemble it for you.
- 01Publish
Share a verified block or a whole project, with its RTL, interfaces, tests, and evidence.
- 02Discover
Search by interface, process, area, and license, and import blocks into a larger design.
- 03Start from a baseline
Extend a proven project instead of starting from a blank file.
- 04Architect knows the catalog
Describe what you need; the Architect recommends existing blocks that fit, and designs the rest from scratch.
- 05Compose SoCs
Snap reusable ASIC blocks onto a bus and grow toward full systems, and later, boards.
- ✓ RTL
- ✓ Interfaces
- ✓ Process support
- ✓ Test results
- ✓ Timing assumptions
- ✓ Physical views
- ✓ Dependencies
- ✓ License
Planned feature, not available yet. Example blocks are illustrative.
One design.
Your choice of destination.
Describe it once. The same RTL, testbench, and goals can stop at simulation, go to silicon, or, soon, run on an FPGA board on your desk.
- SimulateAvailable nowSelf-checking testbench · Waveforms · Goals checked
- FPGAComing soonBoard + pin mapping · Fmax and utilization · Bitstream, then run it
- ASICAvailable nowSynthesis and timing · Place & route, GDS · DRC, LVS, ERC
From verified RTL
to a board in your hand.
- 01Pick a board
The Architect recommends a board that fits your design’s logic, memory, clocks, and I/O, from versioned board manifests, never from guessed pin tables.
- 02Map it to the real world
Ports become buttons, LEDs, UART, PMOD, SPI, and I²C. A reviewable board wrapper and pin constraints are generated for you.
- 03Build with evidence
Yosys, nextpnr, and IceStorm (iCE40 first, then ECP5 and Gowin) report utilization, Fmax against your clock, pins, and logs, checked as goals.
- 04Run it for real
Download the bitstream. Later, a small local helper flashes a connected board and streams its UART output into your browser.
Planned feature, not available yet. The fabric, board, and bars are illustrations, not measurements.