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Registered running-sum monitor · Example, read-only. Explore every file, run, and layout.

A registered running-sum monitor for a sensor stream: simulation, timing, power grid, and a full layout.

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Custom ASIC / SoC · Registered running-sum monitorPersisted
Custom ASIC / SoC · Registered running-sum monitor
Project ID fa688169-19c3-41d2-b355-2e6a5b6b7f9f
Files
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Tapeo · flow mapReady to run

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Each stage shows the files it used and produced, and who made them. Select a stage to open or protect its files, then rerun just that stage or everything after it. Whether your goals are met is in Evaluation.

6 steps with evidence2 skipped / unavailable17 expected outputs missing2 RTL files1 testbenches0 mapped artifactsLatest goal report29 passed
Manufacturing process

AI recommendation: SkyWater 130 nm · HD. You can change the platform and rerun; each platform uses its own libraries and physical-design setup.

Workflow run history

0 saved runs, newest first.

No saved workflow runs yet.

End-to-end development map

Follow the design, files, and evidence through every tool

Branches show retries and optional checks. Select a step to inspect its recorded inputs, outputs, and tool logs below. Pan and zoom to explore the map.

Run status · latest saved evidence
React Flow
RunningPassedCompletedFailedBlockedStale evidenceReady to runSkippedNot run yetNot integrated / installedExpected file missing
Selected stage · 01

RTL simulation

Icarus Verilog

A testbench is present. Run it to establish behavioral evidence.

Inputs used
Who made it · lock = protected from AI repairs
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Outputs and measurements

No output or measurement recorded yet.

Verification layer

Goals and test evidence

29 passed29 checked
testbench_pass= 1 resultpassed

testbench_pass = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
testbench_pass = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
reset_behaviorBehavior: Synchronous active-high reset clears all sample registers, pointer, running sum, sample count, average, quality, and validity outputs. resultpassed

reset_behavior = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
reset_behavior = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
reset_priority_behaviorBehavior: When reset and sample acceptance are simultaneous, synchronous reset takes priority and no sample is stored or accumulated. resultpassed

reset_priority_behavior = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
reset_priority_behavior = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
accepted_sample_updateBehavior: Each accepted sample updates the running sum and increments the sample count until the count saturates at four. resultpassed

accepted_sample_update = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
accepted_sample_update = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
partial_window_validityBehavior: Before four accepted samples, the partial arithmetic average and count are deterministic while average_valid remains deasserted. resultpassed

partial_window_validity = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
partial_window_validity = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
four_sample_averageBehavior: After four accepted samples, the registered average equals the four-sample sum divided by four using a right shift and average_valid is asserted. resultpassed

four_sample_average = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
four_sample_average = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
full_buffer_replacementBehavior: After the buffer is full, each accepted sample replaces the oldest entry, preserves count four, and updates the sliding average. resultpassed

full_buffer_replacement = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
full_buffer_replacement = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
circular_pointer_wrapBehavior: The two-bit circular write pointer wraps after four entries and continues replacing samples in oldest-first order. resultpassed

circular_pointer_wrap = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
circular_pointer_wrap = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
accepted_sample_gatingBehavior: When enable is low or rssi_valid is low, no sample, sum, pointer, count, average, validity, or quality output changes. resultpassed

accepted_sample_gating = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
accepted_sample_gating = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
threshold_classificationBehavior: Quality is poor below 80, moderate from 80 through 159, and good at or above 160. resultpassed

threshold_classification = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
threshold_classification = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
maximum_value_arithmeticBehavior: Four maximum-valued 8-bit samples produce average 255 without running-sum overflow and retain count four. resultpassed

maximum_value_arithmetic = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
maximum_value_arithmetic = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
back_to_back_sample_processingBehavior: One accepted sample is processed on every consecutive clock cycle without loss, duplication, or stale-window arithmetic. resultpassed

back_to_back_sample_processing = 1 result; goal passed.

Measured 1 result · RTL simulation
Icarus Verilog · passed
back_to_back_sample_processing = 1 result; met the goal target.
Used: rtl/rssi_monitor.sv · tb/testbench.sv
setup_slack≥ 0 nspassed

setup_slack = 14.684015 ns; goal passed.

Measured 14.684015 ns · OpenSTA
OpenSTA · passed
setup_slack = 14.684015 ns; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/opensta_timing.tcl · generated/layout/rssi_monitor.openroad.spef
global_route_overflow≤ 0 edgespassed

global_route_overflow = 0 edges; goal passed.

Measured 0 edges · OpenROAD
OpenROAD · passed
global_route_overflow = 0 edges; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
antenna_net_violation_count≤ 0 netspassed

antenna_net_violation_count = 0 nets; goal passed.

Measured 0 nets · OpenROAD
OpenROAD · passed
antenna_net_violation_count = 0 nets; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
antenna_pin_violation_count≤ 0 pinspassed

antenna_pin_violation_count = 0 pins; goal passed.

Measured 0 pins · OpenROAD
OpenROAD · passed
antenna_pin_violation_count = 0 pins; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
antenna_check_complete= 1 resultpassed

antenna_check_complete = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
antenna_check_complete = 1 result; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
placement_utilization50–65 %passed

placement_utilization = 58 %; goal passed.

Measured 58 % · OpenROAD
OpenROAD · passed
placement_utilization = 58 %; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
layout_export_complete= 1 resultpassed

layout_export_complete = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
layout_export_complete = 1 result; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
parasitic_extraction_complete= 1 resultpassed

parasitic_extraction_complete = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
parasitic_extraction_complete = 1 result; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
power_grid_vdd_connected= 1 resultpassed

power_grid_vdd_connected = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
power_grid_vdd_connected = 1 result; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
power_grid_vdd_unconnected_instances≤ 0 instancespassed

power_grid_vdd_unconnected_instances = 0 instances; goal passed.

Measured 0 instances · OpenROAD
OpenROAD · passed
power_grid_vdd_unconnected_instances = 0 instances; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
power_grid_vss_connected= 1 resultpassed

power_grid_vss_connected = 1 result; goal passed.

Measured 1 result · OpenROAD
OpenROAD · passed
power_grid_vss_connected = 1 result; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
power_grid_vss_unconnected_instances≤ 0 instancespassed

power_grid_vss_unconnected_instances = 0 instances; goal passed.

Measured 0 instances · OpenROAD
OpenROAD · passed
power_grid_vss_unconnected_instances = 0 instances; met the goal target.
Used: generated/netlists/rssi_monitor.mapped.v · generated/libraries/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib · constraints/rssi_monitor.sdc · analysis/openroad_flow.tcl
drc_violation_count≤ 0 violationspassed

drc_violation_count = 0 violations; goal passed.

Measured 0 violations · KLayout DRC
KLayout · passed
drc_violation_count = 0 violations; met the goal target.
Used: generated/layout/rssi_monitor.openroad.gds
layout_extraction_complete= 1 resultpassed

layout_extraction_complete = 1 result; goal passed.

Measured 1 result · Magic layout extraction
Magic VLSI · passed
layout_extraction_complete = 1 result; met the goal target.
Used: generated/layout/rssi_monitor.openroad.gds
lvs_match= 1 resultpassed

lvs_match = 1 result; goal passed.

Measured 1 result · Netgen LVS
Netgen LVS · passed
lvs_match = 1 result; met the goal target.
Used: signoff/layout_extracted/rssi_monitor.spice · signoff/reference/rssi_monitor.post-route.v
erc_violation_count≤ 0 violationspassed

erc_violation_count = 0 violations; goal passed.

Measured 0 violations · CVC-RV
CVC-RV · passed
erc_violation_count = 0 violations; met the goal target.
Used: signoff/layout_extracted/rssi_monitor.spice
erc_check_complete= 1 resultpassed

erc_check_complete = 1 result; goal passed.

Measured 1 result · CVC-RV
CVC-RV · passed
erc_check_complete = 1 result; met the goal target.
Used: signoff/layout_extracted/rssi_monitor.spice
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